With the increasingly small size of computer systems and the limited number of signal lines available on a chip, there is demand that multiple devices reside on a single bus. Thus, high speed, multi-drop busses are in widespread use today. This is particularly evident in memory sub-systems, where multiple DIMMs (dual in-line memory modules) reside on a single bus and communicate with a memory controller. In order to ensure reliable, fast transmission of data between the devices, the busses use various transmission line topologies and termination techniques to ensure adequate signal quality.
With multiple DRAM (dynamic random access memory) load devices coupled to a common bus line and driver, negative reflections appear on the bus due to the highly capactive nature of the load devices. Further negative reflections can result from a mismatch between the characteristic impedance of the transmission line and the termination resistor, Rtt, of the transmission line. If not properly handled, these negative reflections result in deleterious effects on signal quality, e.g., loss of available timing margin and/or inadequate voltage margin.
A common technique to handle this problem is to employ a modified version of a daisy-chain bus topology. FIG. 1 illustrates a common bus topology for this purpose. A controller 10 is located at one end of the bus, while DRAM load devices 12, 14, 16 and 18 are situated at uniform intervals, L, along the bus. The bus is terminated at the other end by means of a short trace connecting the last load 18 to Vtt (termination voltage) through the termination resistor Rtt. Vtt is also the reference voltage of the receiver, so that its voltage level is chosen to be half of Vdd (voltage supply of the DRAMs). In order to ensure an adequate DC swing for the receiver, while still maintaining a reasonable size for the driver, the value of Rtt is usually smaller than the characteristic impedance (Zo) of the transmission line.
In general, the equation relating the reflection component V1− generated by an incident waveform V1+ impinging upon a component or device is given by: V1−(t)=ρ(t)V1+, where ρ(t) is an exponential function with a time constant determined by the capacitance value and the impedance in series with it. If ρ(t) takes negative values, the reflected wavefront is also negative, and its maximum amplitude is proportional to the value of V1+ max. A negative value of ρ(t), which gives rise to negative reflections, can occur from a mismatched termination, such that Rtt<Zo, and ρ(t) is a constant negative. A negative value can also occur from a capacitive load across which the voltage changes, such that ρ(t) varies monotonically from −1 to +1 during the period of voltage changing.
The reflections produced travel back down the line towards the driver, and because they are negative, they cause the voltage at the devices they encounter to have a sharp negative trough, acting in the opposite direction to the incident waveform. Such action in the opposite direction causes the voltage waveform at a device to be non-monotonic in the transition region, which results in false switching.
Moreover, if the trace joining the last load 18 to Rtt is short, the negative reflections generated by these two sources of mismatch overlap to produce a much larger negative trough than is produced by each source individually. In this case, even if the voltage waveform has passed through the transition region, the magnitude of the negative reflection may be sufficiently large enough to cause the waveform to ringback below the DC or AC threshold, resulting in false switching or loss of timing margin.
The device most affected is the one closest to the driver (load 12 in FIG. 1). This first device encounters the cumulative effects of the negative voltage reflections produced by the incident wavefront as it passes by all of the remaining devices. A series resistor Rs close to the driver sometimes is used to mitigate this effect. The series resistor reduces the amplitude of V1+, which results in a reduced value of V1−, engendered by both the mismatched termination, as well as the charging (or discharging) capacitor.
While this approach is ubiquitous and has had successful use in certain designs, it has disadvantages. It relies on a trade-off in performance by giving up a fast incident voltage swing (and thus a fast switching time and timing margin) in return for a guarantee of stability (i.e., no non-monotonicity in the transition region.) The series resistance also reduces the steady-state voltage present on the line after the switching, resulting in a loss of steady-state voltage margin.
Accordingly, a need exists for a bus topology for high speed multi-drop, highly capacitive transmission line environments that ensures adequate signal quality. The present invention addresses such a need.